Wrong answer when calling component

To make sure the "sinal_entrada_a" have the right numbers, I've comented the component label_10, changed the "saida" to array_t and write the line:

saida <= sinal_entrada_a;

So I proved checking the simulator that sinal_entrada_a have the right numbers.

If you fell necessary, here's the full code.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE matrizes IS
TYPE array_t IS ARRAY (0 TO 7, 0 to 7) OF STD_LOGIC_VECTOR(0 TO 7);
TYPE array_t2 IS ARRAY (0 TO 7, 0 to 7) OF STD_LOGIC_VECTOR(0 TO 11);
TYPE array_t3 IS ARRAY (0 TO 7, 0 to 7) OF STD_LOGIC_VECTOR(0 TO 14);
TYPE array_t4 IS ARRAY (0 TO 15, 0 to 15) OF STD_LOGIC_VECTOR(0 TO 7);
END matrizes;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.matrizes.all;
ENTITY rct_512 IS
PORT (
clk: IN STD_LOGIC;
entrada: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
saida: OUT array_t2
);
END rct_512;
ARCHITECTURE comportamento OF rct_512 IS
------------------------------------------
----------------SIGNAL--------------------
SIGNAL sinal_entrada: array_t4;
signal sinal_entrada_a: array_t;
SIGNAL clk_var: integer range 0 to 256 :=0;
SIGNAL i, ii: integer range 0 to 15 :=0; 
signal done: std_logic:='0';
-------------------END--------------------
COMPONENT rct IS
PORT (
clk: IN STD_LOGIC;
entrada: IN array_t;
saida: OUT array_t2
);
END COMPONENT;
BEGIN
--------------Import Entrada serial mode----
Process (clk)
Begin
    if clk'event AND (clk='1') then
    if done='0' then
        if clk_var=256 then done<='1'; end if;
            if clk_var<256 then
        
            clk_var<=clk_var+1;                        
            sinal_entrada(i, ii)<=entrada;
            ii<=ii+1;
        
                    if (ii=15) then
                    i<=i+1;
                    ii<=0;
                    end if;            
        end if;
        
            else    ------take 8x8 matrix from sinal_entrada
        
                for i in 0 to 7 loop
                    for j in 0 to 7 loop
                        sinal_entrada_a(i, j) <= sinal_entrada(i, j);
                    end loop;
                end loop;        
       end if;
    end if;
end process;
--saida <= sinal_entrada_a;
label_10: rct PORT MAP (clk, sinal_entrada_a, saida);
END comportamento;

The "if" part is a little confusing but is working. It intend to import 256 bytes (16x16 matrix) from "entrada" via serial.

And the "else" part is to take the first 8x8 block from the matrix after all the samples is imported. That 8x8 block is the input of the component.

Thank You!