Writing to DDR3 with bypassing NIOS2

Hello everybody

i have been now struggling for a week. I have a Qsys design, with nios2/f, ddr3 and onchip memory. I have implemented a tightly coupled instruction and data bus.

I can compile and download my firmware with no problem. When i download nios2 software i can see that it is downloaded and also it is running. All the messages are displayed in the nios2 command line.

What i want to do now is add a n external port so that i can write to ddr3 directly. I tried the avalon master template and it doesnt work. I wrote my own vhdl file that is very simple

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity mem_access is
 
  generic (
    BYTEENABLEWIDTH : integer := 4;     -- byte enable width
    ADDRESSWIDTH    : integer := 32;    -- width of the address bus
    DATAWIDTH       : integer := 32);   -- width of data bus
 
  port (
    csi_mem_clk          : in  std_logic;  -- clock of the memory controller
    csi_mem_reset_n      : in  std_logic;  -- reset of the memory controller
    avm_mem_waitrequest_n: in  std_logic;  -- wait request issued by memory
	avm_mem_beginbursttransfer : out std_logic;  -- read command to the memory
    avm_mem_address      : out std_logic_vector(ADDRESSWIDTH-1 downto 0);  -- address of the data in the memory
    avm_mem_readdatavalid: in  std_logic;  -- wait request issued by memory
	avm_mem_readdata     : in  std_logic_vector(DATAWIDTH-1 downto 0);  -- read data from memory
    avm_mem_writedata    : out std_logic_vector(DATAWIDTH-1 downto 0);  -- write data to the memory
    avm_mem_byteenable   : out std_logic_vector(BYTEENABLEWIDTH-1 downto 0);  -- byte to write to memory
    avm_mem_read         : out std_logic;  -- read command to the memory
    avm_mem_write        : out std_logic;  -- write command to the memory
    avm_mem_burtscount   : out std_logic_vector(DATAWIDTH/4-1 downto 0);  -- byte to write to memory
    
    cso_ctrl_clk         : in std_logic;  -- out clock from the NIOS fabric
    rso_ctrl_reset_n     : in std_logic;  -- out reset from the NIOS fabric
    avs_mem_writedata   : in  std_logic_vector(DATAWIDTH-1 downto 0);  -- data to be written from FPGA fabric
    avs_mem_readdata    : out std_logic_vector(DATAWIDTH-1 downto 0);  -- read data from memory
    avs_mem_burtscount   : in std_logic_vector(DATAWIDTH/4-1 downto 0);  -- byte to write to memory
    avs_mem_beginbursttransfer : in std_logic;  -- read command to the memory
    avs_mem_readdatavalid: out  std_logic;  -- wait request issued by memory
	avs_mem_address     : in  std_logic_vector(ADDRESSWIDTH-1 downto 0);  -- address of the data in the memory
    avs_mem_byteenable  : in  std_logic_vector(BYTEENABLEWIDTH-1 downto 0);  -- byte to write to memory
    avs_mem_write       : in  std_logic;  -- write command to the memory
    avs_mem_read        : in  std_logic;  -- read command to the memory
    avs_mem_waitrequest_n : out std_logic   -- wait request issued by memory
    );
end entity mem_access;
 
architecture top of mem_access is
 
begin  -- architecture top
 
  avs_mem_waitrequest_n <= avm_mem_waitrequest_n;
  avm_mem_beginbursttransfer <= avs_mem_beginbursttransfer;
  avm_mem_address      <= avs_mem_address;
  avs_mem_readdatavalid <= avm_mem_readdatavalid;
  avs_mem_readdata    <= avm_mem_readdata;
  avm_mem_writedata    <= avs_mem_writedata;
  avm_mem_byteenable   <= avs_mem_byteenable;
  avm_mem_read         <= avs_mem_read;
  avm_mem_write        <= avs_mem_write;
  avm_mem_burtscount <= avs_mem_burtscount;
  
 
end architecture top;

The slave port "avs_" is exported and master port "avm_" is connected directly to ddr3.

Can some one please tell me what i am doing wrong.

In Nios2 software i declare

volatile int* volatile pFlag = (int*)0x03000000;

This is my address to which i want to write from vhdl. Then in the NIOS2 i check if the flag is 1 or 0.

The check show that 1pFlag is always 0.

I dont know why.

Did anyone try anything similar. How did you resolve this problem?

Thank you