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MPaso's avatar
MPaso
Icon for New Contributor rankNew Contributor
7 years ago

Writing to DDR3 with bypassing NIOS2

Hello everybody i have been now struggling for a week. I have a Qsys design, with nios2/f, ddr3 and onchip memory. I have implemented a tightly coupled instruction and data bus. I can compile and...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
7 years ago

Clock and reset are for the bridge itself, so both interfaces (master and slave). Just use the same clock and reset you're using for other components.