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Altera_Forum
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15 years ago

working with Quartus 8+Synplify DSP + Synplify PRO

Hi all,

I'm working on a undergraduate final project, and I use SynplifyDSP to implement a video improvement algorithm.

The problem I faced - In my algorithm I have to access external memory in between two parts of the algorithm, so to do so I divided my Synplify DSP project into several blocks (in several files),

I then synthesized each one separately (firstly I created VHDL in Synplify DSP and then went to Synplify PRO and ran a synthesis there).

This have created several VQM's that I then inserted into Quartus.

When I then compile the project, I get errors -

things like undeclared pins etc. I think that this happens because Synplify DSP creates blocks with same names when working on different files.

I tried to combine the entire project into one file, but then when I choose retiming in synplify I didn't get the frequency I need (but when I synthesize each part on its own, I do get it to work fast enough).

My only conclusion - I must find a way to force the SynplifyDSP\PRO to generate different names, so I would be able to combine it all in Quartus, and thus hold the minimum frequency I need.

any ideas on how I can to that?

I would really appreciate any help...

thanks,

Bulzeye

P.S. sorry for my English...

33 Replies

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    using the single vqm implementation - the simulation works.

    as regard to the input/output constraint - is it possible to constrain all the input/output at once?

    and also - how can I estimate this delay? and what if I push registers in Quartus between the blocks (in and out) - will they "stay put" there? (and then I will avoid constraining the inputs and outputs) - I think it would be ok. what do you think?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    using the single vqm implementation - the simulation works.

    as regard to the input/output constraint - is it possible to constrain all the input/output at once?

    and also - how can I estimate this delay? and what if I push registers in Quartus between the blocks (in and out) - will they "stay put" there? (and then I will avoid constraining the inputs and outputs) - I think it would be ok. what do you think?

    --- Quote End ---

    Hi,

    you can set a default delay:

    define input_delay -default 1.00 -ref {clkb:r}

    When you import the netlist and you run a "simple" P&R run Quartus will not move your register. In case you use register retiming in Quartus the registers maybe will be moved, but Quartus will take care of the timing.

    BTW: Did you check your reset and clock connectivity ?

    Kind regards

    GPK
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    Hi,

    you can set a default delay:

    define input_delay -default 1.00 -ref {clkb:r}

    When you import the netlist and you run a "simple" P&R run Quartus will not move your register. In case you use register retiming in Quartus the registers maybe will be moved, but Quartus will take care of the timing.

    BTW: Did you check your reset and clock connectivity ?

    Kind regards

    GPK

    --- Quote End ---

    ok - I'll try it.

    and I did check the connectivity.

    thanks!