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Altera_Forum's avatar
Altera_Forum
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15 years ago

working with Quartus 8+Synplify DSP + Synplify PRO

Hi all, I'm working on a undergraduate final project, and I use SynplifyDSP to implement a video improvement algorithm. The problem I faced - In my algorithm I have to access external memor...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Hi,

you can set a default delay:

define input_delay -default 1.00 -ref {clkb:r}

When you import the netlist and you run a "simple" P&R run Quartus will not move your register. In case you use register retiming in Quartus the registers maybe will be moved, but Quartus will take care of the timing.

BTW: Did you check your reset and clock connectivity ?

Kind regards

GPK

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ok - I'll try it.

and I did check the connectivity.

thanks!