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using the single vqm implementation - the simulation works.
as regard to the input/output constraint - is it possible to constrain all the input/output at once?
and also - how can I estimate this delay? and what if I push registers in Quartus between the blocks (in and out) - will they "stay put" there? (and then I will avoid constraining the inputs and outputs) - I think it would be ok. what do you think?
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Hi,
you can set a default delay:
define input_delay -default 1.00 -ref {clkb:r}
When you import the netlist and you run a "simple" P&R run Quartus will not move your register. In case you use register retiming in Quartus the registers maybe will be moved, but Quartus will take care of the timing.
BTW: Did you check your reset and clock connectivity ?
Kind regards
GPK
Honored Contributor
