Forum Discussion

Xuzeng_'s avatar
Xuzeng_
Icon for New Contributor rankNew Contributor
6 months ago

why tx_pll_pocked and rx_cdr_pocked is always Not locked.

There is my some code about the clk,and the signal "CLK_QSFP_0_P" is connected to the REFCLK pin.

When i use the tool "system console"to test the prbs,it's always not work.

Platform

5 Replies

  • Ash_R_Intel's avatar
    Ash_R_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 months ago

    Hi,

    This is too less information to debug.

    Mainly you should check if the signal CLK_QSFP_0_P is getting the correct frequency of clock as per the configuration in the syspll IP or not.

    For the Rx side, ensure that the pin is receiving data at correct rate as configured in the F-tile IP.


    Regards


    • Xuzeng_'s avatar
      Xuzeng_
      Icon for New Contributor rankNew Contributor
      6 months ago

      Hi,

      I need to debug the QSFP interface. I have verified that:

      1. The frequency of CLK_QSFP_0_P is correctly set to 156.25 MHz

      2. The proper reference clock source has been selected

      Current clock configuration status:Hardware connection for CLK_QSFP_0_P is physically routed to quad2_ch5 (GT Quad 2, Channel 5).

  • Ash_R_Intel's avatar
    Ash_R_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 months ago

    Hi,

    For the TX_pll_locked, can you check the "Auto Refresh Tx Status Above" option and see what you are getting?

    Make sure that the Refclk5 is getting a stable and free running 156.25MHz during run time from the board.

    Try clicking on the "Tx Reset FGT PMA" button and see if it makes any difference.


    Rx side, as said earlier, please ensure that data is properly received from the board. If you are not sure of that, once your Tx side is up, try setting the internal serial loopback within the FPGA. For this, set "Loopback mode" to TX2RXBUF value. You can also make use of PRBS pattern generator and checker for the data.


    Regards


    • Xuzeng_'s avatar
      Xuzeng_
      Icon for New Contributor rankNew Contributor
      6 months ago

      Hi Ash,

      Thank you for your response. Currently, my clock is locked. However, when I click TX PRBS Start, followed by RX PRBS Start, the RX PRBS stops almost immediately, and the Message window displays:verflow condition detected.

      This image illustrates the issue I encountered.

      And this shows the clock configuration of the IP core and its interface connections.

  • Ash_R_Intel's avatar
    Ash_R_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 months ago

    Hi,

    Thanks for the update. From the screen shot, I cannot figure out whether any internal or external loopback is enabled or not. That is a way to ensure whatever you are transmitting is reaching the Rx pins.

    As I mentioned earlier, basically you need to make sure that the data is being received at the right rate on the receiver pin.


    Regards