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Xuzeng_'s avatar
Xuzeng_
Icon for New Contributor rankNew Contributor
7 months ago

why tx_pll_pocked and rx_cdr_pocked is always Not locked.

There is my some code about the clk,and the signal "CLK_QSFP_0_P" is connected to the REFCLK pin. When i use the tool "system console"to test the prbs,it's always not work.
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Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
7 months ago

Hi,

For the TX_pll_locked, can you check the "Auto Refresh Tx Status Above" option and see what you are getting?

Make sure that the Refclk5 is getting a stable and free running 156.25MHz during run time from the board.

Try clicking on the "Tx Reset FGT PMA" button and see if it makes any difference.


Rx side, as said earlier, please ensure that data is properly received from the board. If you are not sure of that, once your Tx side is up, try setting the internal serial loopback within the FPGA. For this, set "Loopback mode" to TX2RXBUF value. You can also make use of PRBS pattern generator and checker for the data.


Regards


  • Xuzeng_'s avatar
    Xuzeng_
    Icon for New Contributor rankNew Contributor
    7 months ago

    Hi Ash,

    Thank you for your response. Currently, my clock is locked. However, when I click TX PRBS Start, followed by RX PRBS Start, the RX PRBS stops almost immediately, and the Message window displays:verflow condition detected.

    This image illustrates the issue I encountered.

    And this shows the clock configuration of the IP core and its interface connections.