Why do all four versions of this verilog code have the save timing-simulation waveforms?

Hi,

This might be a bug. Can you share your .qar file here?

To do this, go to Project->Archive Project.

Regards,

Nurina

Hi,

Do you have any updates?

Regards,

Nurina

Hello,

no sure what you are specifically asking.

Why do you expect different timing results for the codes?
Timing control statements in assignments are only effective in functional simulation or stimulus generation in testbenches.
They have no effect on hardware synthesis. Timing simulation is evaluating the behaviour of synthesized logic, timing control is ignored here.

Best regards

Frank

If you are going to ask a question you need to provide a lot of supporting info if you want more than generic responses.

What version of Quartus?

What platform (ie, Windows, Linux, etc) and version?

What simulator (Questa I believe) and version?

Can you make a test bench that instantiates all the modules at once and runs them in parallel to display exact waveforms of each?

You say they are the 'same' but we really can't validate that assertion in the data you present.

Hi,

As mentioned in above comments, delay cannot be synthesized, that's why you see the same waveforms.

However, you can use this in testbenches.

Regards,

Nurina

Hi,

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Regards,

Nurina