Why do all four versions of this verilog code have the save timing-simulation waveforms?

Hello,

no sure what you are specifically asking.

Why do you expect different timing results for the codes?
Timing control statements in assignments are only effective in functional simulation or stimulus generation in testbenches.
They have no effect on hardware synthesis. Timing simulation is evaluating the behaviour of synthesized logic, timing control is ignored here.

Best regards

Frank