Chris24New Contributor3 years agoWhy do all four versions of this verilog code have the save timing-simulation waveforms? Why do all four versions of this verilog code have the save timing-simulation waveforms? 01.png14 KB02.png9 KB03.png9 KB04.png10 KBwaveform.png33 KB
NurinaRegular Contributor3 years agoHi,This might be a bug. Can you share your .qar file here?To do this, go to Project->Archive Project.Regards,Nurina
Recent DiscussionsInvalid license key (inconsistent authentication code)Regarding the issue of UFM not startingram retimingReset Release IP for Agilex needs Stratix 10 device files installed!Licensing ‘Know-How’ Guide
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