When to deassert a signal?

process (clk, reset) begin
if (reset ='1') then
   reg <= '0';
elsif (clk'event and clk='1') then
   reg <= valid;   
end if;
--falling edge detect. This produces a one clk wide pulse when valid goes from '1' to '0'
valid_fe <= reg and not valid;

I'm not sure I understand how this works. To me it looks like you're checking for valid and not valid at the same time

Ok, I think I understand how it should work, but I don't understand why it still doesn't work. The process statement makes it so that the reg stores the value of valid, and then you're comparing the old value of valid with the new value of valid so you detect the falling edge. Here's how I tried to implement it, but it doesn't work:

library ieee;
use ieee.std_logic_1164.all;
--This file is responsible for reading in frames and storing them
entity FrameHolder2 is
	port
	(
		clk,reset: in std_logic;--clock and reset inputs
		input: in std_logic;--the serial input on which the ethernet frames arrive
		valid: in std_logic;--the valid signal which lets us know when an ethernet frame is valid
		startout: out std_logic;--a test output to let us trace when we are storing ethernet information
		storeout: out std_logic;--a test output to let us know when we would commit the stored data
		output: out std_logic--the output ethernet stream
	);
end FrameHolder2;
architecture structure of FrameHolder2 is
	signal prehold: std_logic_vector(63 downto 0);--holds the preamble
	signal start: std_logic;--lets us know if we're ready to start storing the ethernet frame
	signal reg: std_logic;--temporary register to help detect when valid goes to '0'
	signal valid_fe: std_logic;--valid falling edge, lets us know when valid goes to '0' from '1'
	
	component rshift8byte is --8 byte right shift register for holding onto the preamble
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		enable		: IN STD_LOGIC ;
		shiftin		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
	);
	end component;
begin	
	process (clk, reset) 
	begin
	if (reset ='1') then
		reg <= '0';
	elsif (clk'event and clk='1') then
		reg <= valid;   --this detects when valid goes from '1' to '0'
	end if;
	end process;
	stage0: rshift8byte port map(reset,clk,not start,input,prehold);
	
valid_fe <= '1' when reg = '1' and valid = '0'; --detects when valid goes from '1' to '0', we need to do this 
--because valid goes high at some point during the preamble, and goes low when the frame is received.
--We need to know when we are done receiving a frame and this occurs on the falling edge of valid.
start <= '1' when prehold = "1101010101010101010101010101010101010101010101010101010101010101" and valid_fe = '0' else '0';--start storing the ethernet frame until we get a falling edge of valid
storeout <= '1' when valid_fe = '1';
startout <= start;
end structure;

I'm also assuming the VALID signal is synchronous to the CLK clock domain. If not you need to synchronize it first.

library ieee;
use ieee.std_logic_1164.all;
--This file is responsible for reading in frames and storing them
entity FrameHolder2 is
	port
	(
		clk,reset: in std_logic;--clock and reset inputs
		input: in std_logic;--the serial input on which the ethernet frames arrive
		valid: in std_logic;--the valid signal which lets us know when an ethernet frame is valid
		startout: out std_logic;--a test output to let us trace when we are storing ethernet information
		storeout: out std_logic;--a test output to let us know when we would commit the stored data
		output: out std_logic--the output ethernet stream
	);
end FrameHolder2;
architecture structure of FrameHolder2 is
	signal prehold: std_logic_vector(63 downto 0);--holds the preamble
	signal start: std_logic;--lets us know if we're ready to start storing the ethernet frame
	signal reg: std_logic;--temporary register to help detect when valid goes to '0'
	signal valid_fe: boolean;--valid falling edge, lets us know when valid goes to '0' from '1'
	
	component rshift8byte is --8 byte right shift register for holding onto the preamble
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		enable		: IN STD_LOGIC ;
		shiftin		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
	);
	end component;
begin	
	process (clk, reset) 
	begin
	if (reset ='1') then
		reg <= '0';
	elsif (clk'event and clk='1') then
		reg <= valid;   --this detects when valid goes from '1' to '0'
	end if;
	end process;
	stage0: rshift8bit port map(reset,clk,not start,input,prehold);
	--stage1: something port map(reset,clk,start and valid,input,something);
	
valid_fe <= reg='1' and valid='0'; --detects when valid goes from '1' to '0', we need to do this 
--because valid goes high at some point during the preamble, and goes low when the frame is received.
--We need to know when we are done receiving a frame and this occurs on the falling edge of valid.
start <= '1' when prehold = "1101010101010101010101010101010101010101010101010101010101010101" and not valid_fe else '0';--start storing the ethernet frame until we get a falling edge of valid
storeout <= '1' when valid_fe else '0';
startout <= start;
end structure;

Im not sure I like this statement:

start <= '1' when prehold = "1101010101010101010101010101010101010101010101010101010101010101" and not valid_fe else '0';--start storing the ethernet frame until we get a falling edge of valid

Won't I need a state machine with 64 states then?

no you shouldnt.

.......
  constant WORD_TO_LOOK_FOR : std_logic_vector := "1101010101010101010101010101010101010101010101010101010101010101";
  signal rom_addr : integer range 0 to WORD_TO_LOOK_FOR'length-1;
  type state_t is (wait_for_start, collecting_word);
  signal state : state_t;
begin
...
process(clk, reset)
begin
  if reset = '1' then
    state <= wait_for_start;
    rom_addr <= 0;
    start <= '0';
    
  elsif rising_edge(clk) then
    
    start <= '0';
    case state is
      when wait_for_start => 
        
        if valid = '1' then
          if input = WORD_TO_LOOK_FOR(0) then
            rom_addr <= rom_addr + 1;
            state <= collecting_word
            
          else
            state <= wait_for_start;
          end if;
        else
          state <= wait_for_start;
        end if;
          
      when collecting_word =>
        
        if valid = '1' then
          if input = WORD_TO_LOOK_FOR(rom_addr) then
          
            if rom_addr = WORD_TO_LOOK_FOR'length-1 then
              --got entire word, start something off
              start <= '1';
              state <= wait_for_start;
            else
              
              --waiting for entire word
              state <= collecting_word;
              
              --address increment - looking for the next bit in sequence
              rom_addr <= rom_addr + 1;
            end if;
          
          else
            --sequence broken, go back to start
            state <= wait_for_start;
            rom_addr <= 0;
          end if;
        
        else
          
          --hold in this state
          state <= collecting_word;
        end if;
    end case;
  end if;
    
end process;
          

That makes sense, thanks!