Honored Contributor
Honored Contributorno you shouldnt.
You could hold the sequence in a small rom and use a counter to address it so you do something like this and be able to run alot faster (ie faster clock):
.......
constant WORD_TO_LOOK_FOR : std_logic_vector := "1101010101010101010101010101010101010101010101010101010101010101";
signal rom_addr : integer range 0 to WORD_TO_LOOK_FOR'length-1;
type state_t is (wait_for_start, collecting_word);
signal state : state_t;
begin
...
process(clk, reset)
begin
if reset = '1' then
state <= wait_for_start;
rom_addr <= 0;
start <= '0';
elsif rising_edge(clk) then
start <= '0';
case state is
when wait_for_start =>
if valid = '1' then
if input = WORD_TO_LOOK_FOR(0) then
rom_addr <= rom_addr + 1;
state <= collecting_word
else
state <= wait_for_start;
end if;
else
state <= wait_for_start;
end if;
when collecting_word =>
if valid = '1' then
if input = WORD_TO_LOOK_FOR(rom_addr) then
if rom_addr = WORD_TO_LOOK_FOR'length-1 then
--got entire word, start something off
start <= '1';
state <= wait_for_start;
else
--waiting for entire word
state <= collecting_word;
--address increment - looking for the next bit in sequence
rom_addr <= rom_addr + 1;
end if;
else
--sequence broken, go back to start
state <= wait_for_start;
rom_addr <= 0;
end if;
else
--hold in this state
state <= collecting_word;
end if;
end case;
end if;
end process;
