What is usage of "generate" in Verilog?

I am confused by the usage of "generate" in Verilog. I checked it online, find some demo codes like:

genvar index;

generate

for (index= 0;index < 64;index = index+1) begin : dq_delay

WireDelay#

(

.Delay_g (TPROP_PCB_DATA),

.Delay_rd (TPROP_PCB_DATA_RD),

.ERR_INSERT ("OFF")

)

u_delay_dq

(

.A (ddr3_dq_fpga[index]),

.B (ddr3_dq_sdram[index]),

.reset (~i_rst_p),

.phy_init_done (init_calib_complete)

);

end

endgenerate

But what is the difference between using "generate" and only use "For" without "generate"? If I wrote the above codes as:

for (index= 0;index < 64;index = index+1) begin : dq_delay

WireDelay#

(

.Delay_g (TPROP_PCB_DATA),

.Delay_rd (TPROP_PCB_DATA_RD),

.ERR_INSERT ("OFF")

)

u_delay_dq

(

.A (ddr3_dq_fpga[index]),

.B (ddr3_dq_sdram[index]),

.reset (~i_rst_p),

.phy_init_done (init_calib_complete)

);

end

No "generate", what is the difference?

Thanks.