What is usage of "generate" in Verilog?

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You still need the genvar index; statement in either situation.

Verilog 2005 made the generate/endgenerate keywords optional. Since the for loop appears outside of a procedural context, the extra keywords are unnecessary. The compiler is able to figure out that a for/if/case statement in a module context outside a procedural context is a generate block.

Verilog is a language full of implicit defaults. But sometimes it is better to document your intent by putting the extra keywords in there.

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Thanks, dave_59. So that means two codes I wrote are same in Verilog 2005, right?

Another question, you mentioned "for/if/case statement in a module context outside a procedural context is a generate block." Do you mean "if" or "case" out of "always"? I have never see that.

Thanks.