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Altera_Forum
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13 years ago

What is usage of "generate" in Verilog?

I am confused by the usage of "generate" in Verilog. I checked it online, find some demo codes like: genvar index; generate for (index= 0;index < 64;index = index+1) begin : ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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There are examples in the LRM section I mentioned, particularity a for nested inside a case generate. Don't have a copy of the LRM? get one (go.mentor.com/get-1800)!

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Thanks. I should get one. Do you know what is the latest version?