Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

What is usage of "generate" in Verilog?

I am confused by the usage of "generate" in Verilog. I checked it online, find some demo codes like: genvar index; generate for (index= 0;index < 64;index = index+1) begin : ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

--- Quote Start ---

Yes, those construct have always been available together with for as a generate construct. See LRM 27.5 conditional generate constructs.

--- Quote End ---

Thanks, dave_59. I am still confused by this. Could you please give an example that "if/case" out of "always"? They must work with generate together, right? I mean if "if/case" is out of "always", "generate" can't be neglected like "for" statement. right?