Altera_Forum
Honored Contributor
12 years agoWhat is the way to lead the OpenCL SDK compiler to reduce kernel logic utilization ?
Hello friends,
I am working on implementing a video processing design on an FPGA using OpenCL . When generating reports for my design,I get 40% of logic utilization and 23 Mworkitems/s as throughput .With this configuration, the throughput we have is too high for the application we are implementing (we only need 3 Mworkitems/s for the application ) .We assume there is no use having a too faster design if the FPGA utilization is too high. The solution would be to lead the compiler to reduce the logic utilization by decreasing the throughput (for example, we can get 30% of logic utilization and 5 Mworkitems/s as throughput, what would be correct for our design) But when using the "--util" threshold option (aoc -c kernels.cl --util 30 --report) , there is no effect : the logic utilization stays constant and the throughput no longer decrease. So, what is the the way to reduce logic utilization even if the throughput is decreased ? Any suggestions ? Thanks