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Altera_Forum
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12 years ago

What is the way to lead the OpenCL SDK compiler to reduce kernel logic utilization ?

Hello friends, I am working on implementing a video processing design on an FPGA using OpenCL . When generating reports for my design,I get 40% of logic utilization and 23 Mworkitems/s as throu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

After looking at the programming/optimization guides it looks like you should try -O3 --util 30. Another possibility would be to prevent any loop unrolling by using a smaller loop unroll factor, possibly even one to prevent any unrolling, e.g.,# pragma unroll 1.