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Altera_Forum
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12 years ago

What is the way to lead the OpenCL SDK compiler to reduce kernel logic utilization ?

Hello friends, I am working on implementing a video processing design on an FPGA using OpenCL . When generating reports for my design,I get 40% of logic utilization and 23 Mworkitems/s as throu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi sean.settle,

I think this that not solve my issue .There is no optimization attribute in my kernel (no unroll, no vectorization, no replication) .So, the compiler may set these optimization value to 1.

However, I want the compiler to use the trade-off between performance and logic utilization to reduce my logic utilization.