s002wjhwen
New Contributor
8 hours agolog signal to signal tap
is there system verilog syntax that can mark a signal for ILA in signal tap?
for example Xilinx Vivado has
(* mark_debug = "true" *) logic [7:0] dbg_sig; which will put it in the ILA
is there system verilog syntax that can mark a signal for ILA in signal tap?
for example Xilinx Vivado has
(* mark_debug = "true" *) logic [7:0] dbg_sig; which will put it in the ILA