Forum Discussion
s002wjhwen
New Contributor
New Contributorlog signal to signal tap
is there system verilog syntax that can mark a signal for ILA in signal tap? for example Xilinx Vivado has (* mark_debug = "true" *) logic [7:0] dbg_sig; which will put it in the ILA
KennyT_altera
Super Contributor
Super ContributorAs we do not receive any response from you on the previous reply that we have provided, we shall close this thread.
