Warning: No Clocks Defined in Design

I think, the problem is that an external clock input is missing. I'm not sure, whether you can use an internal pll as clock without any external clock.

I connected the input of the pll to the pin associated with the system clock, does that not count as an external clock?

How do you connect the PLL generated clocks in your design? If they aren't used by any existing part of the design (= some logic, that has output signals), they are removed during synthesis.

The output of the pll is connected to the clocks in the shift registers. I just need one clock in my design to run at 200kHz, and looking at my .bdf it looks like I have that, but the same "no clock" error is popping up.

There should be more errors in compiler log, cause no Altera PLL is able to generate an output frequency of 200 kHz.

There are more errors in the compiler log: "Design contains 1 input pin(s) that do not drive logic ("No output dependent on the input pin 'CLK'")" & "Synthesized away the following node(s): clk[0] (the output of the PLL)." So I now understand why I get the "no clock defined" error, but I don't understand why the program thinks the clock doesn't drive logic when it is used as an input into the shift registers.

O.K., I have to correct myself, starting with Cyclone III and Stratix II, Altera PLLs have a postcounter cascading feature and can generate rather low frequencies. 200 kHz is possible with 20 MHz input. Sorry for causing confusion in this point.

I am building a 8 tap correlator, so the outputs of the shift registers are being used as inputs into an lpm_mult megafunction and also as inputs into the next shift register. So I just wired the output of each shift register to the input of its respective multiplier megafunction and the next shift regsiter.

If you don't have unconnected reset inputs of any Megafunction, forgot about it now. Regarding the correlator design, what's the final output of the design? I assume, it has one. But it may be the case, that it's constant due to any design error. Then the complete logic may be removed during synthesis.

I attached some screen shots of the .bdf file. but here is a brief description. My 8-tap correlator consists of 8 right-shift registers, 8 multipliers, a parallel adder, and a PLL. I start with an 8-bit input pin which is fed into the first multiplier and the first shift register. In the first multiplier, the input is multiplied by a constant and the output of the first multiplier is fed into the parallel adder. The output of the first shift register is fed into the second multiplier and the second shift register. The right shifted input is fed into the 2nd multiplier and multiplied by a different constant and the output of the 2nd multiplier is fed into the same parallel adder. This pattern continues for 8 multipliers. The output of the parallel adder is 8 bits and assigned to pins on the chip. The input of the PLL is connected to the pin assigned to the system clock and the output of the PLL is connect to each clock input of the 8 shift registers.