Honored Contributor
Honored ContributorI attached some screen shots of the .bdf file. but here is a brief description. My 8-tap correlator consists of 8 right-shift registers, 8 multipliers, a parallel adder, and a PLL. I start with an 8-bit input pin which is fed into the first multiplier and the first shift register. In the first multiplier, the input is multiplied by a constant and the output of the first multiplier is fed into the parallel adder. The output of the first shift register is fed into the second multiplier and the second shift register. The right shifted input is fed into the 2nd multiplier and multiplied by a different constant and the output of the 2nd multiplier is fed into the same parallel adder. This pattern continues for 8 multipliers. The output of the parallel adder is 8 bits and assigned to pins on the chip. The input of the PLL is connected to the pin assigned to the system clock and the output of the PLL is connect to each clock input of the 8 shift registers.
I really don't see where my logic is wrong. I have the following warnings: the output of the PLL was synthesized away, two input pins do not drive logic (the least sig bit of the input into the first multiplier and the input into the PLL), one output pin is stuck to gnd (just the most sig bit of the output of the parallel adder), no clock defined in the design, and at least one filter could not be matched with a register. I think the warnings may be connected somehow. Any help would be greatly appreciated! I've looked in the tutorials and manuels and they have not helped. Thanks! https://www.alteraforum.com/forum/attachment.php?attachmentid=995 https://www.alteraforum.com/forum/attachment.php?attachmentid=996 https://www.alteraforum.com/forum/attachment.php?attachmentid=997
