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Altera_Forum
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16 years ago

Warning: No Clocks Defined in Design

Everytime I compile my design in the Quartus II software (the web edition), I get a warning that states "No clocks defined in design" even though in my .bdf file I have an altpll block with the input...
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Altera_Forum
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16 years ago

O.K., I have to correct myself, starting with Cyclone III and Stratix II, Altera PLLs have a postcounter cascading feature and can generate rather low frequencies. 200 kHz is possible with 20 MHz input. Sorry for causing confusion in this point.

So there must be another reason why the clock input is removed in synthesis. Did you connect also the shift register in and outputs to pins? Another possible reason is, when the logic is kept in reset due to an existing but unconnected reset function.