Warning: No Clocks Defined in Design

There are more errors in the compiler log: "Design contains 1 input pin(s) that do not drive logic ("No output dependent on the input pin 'CLK'")" & "Synthesized away the following node(s): clk[0] (the output of the PLL)." So I now understand why I get the "no clock defined" error, but I don't understand why the program thinks the clock doesn't drive logic when it is used as an input into the shift registers.

I was able to output a 200k frequency by dividing a 20MHz frequency by 100. Although, if I want to use the system clock (the one on the FPGA) will I have to change the inclk0 frequency to the frequency of the system clock (50MHz) and divide by 250? Can I do that? I looked in the documentation and found the particular pin connected to the system clock, so I thought it was possible.

It should be noted, I am extremely new to Quartus, and I have been trying to teach myself the program, so my questions may seem basic.