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NoahHuguenin's avatar
NoahHuguenin
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10 months ago

vlog-7 "Failed to open design unit file in read mode" error during simulation for Agilex7 board

Good day, I am trying to simulate an HLS for an Agilex7 device. I'm using Quartus Prime Pro 24.2, and the corresponding versions of Questa - Intel FPGA Edition and HLS Compiler. Running on a Windo...
Simulation
NoahHuguenin's avatar
NoahHuguenin
Icon for Occasional Contributor rankOccasional Contributor
10 months ago

Hello @BoonBengT_Altera

Thank you for the recommendations, I will work on that to hopefully provide a design which I can share to see if the error can be replicated.

Meanwhile, while trying to simulate a parallel project, I received a similar error:

# ** Error: (vlog-7) Failed to open design unit file "../../../components/channel_compensation/channel_compensation/channel_compensation_internal_10/sim/channel_compensation_i_iowr_bl_eststream0000hannel_compensation0.sv" in read mode.
# No such file or directory. (errno = ENOENT)

This time it is apparent that the unit involved has something to do with a Stream Interface (estStream) for my channel_compensation component, but again, this file does seem to exist in the specified folder.

Perhaps this indicates that the previous error was not an isolated problem.

In any case, I hope to be back soon with a design to share.

Thank you and regards,

Noah