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BoonBengT_Altera
Joined 6 years ago
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Re: Agilex 5 GTS Reference Clock Buffer Protection
Hi sbj Please find the below response on the question you have: The protection mechanism cannot be disabled or permanently overridden, and it automatically turns off the GTS input reference clock buffer when clock activity is absent or outside the 25–380 MHz detection range (Input Reference Clock Buffer Protection). The best way to avoid buffer shutoff is to keep the reference clock continuously present and toggling within the supported frequency range (Aging Issue on Unconnected/Used GTS Input Reference Clock Pins). If the clock stops, recovery requires either device reconfiguration or a buffer re-enable request through the register method or optional status/control ports (Input Reference Clock Buffer Protection). From Quartus Prime 24.3.1 onward, the device provides automatic aging protection, but user logic must still manually re-enable the buffer after the reference clock is restored (Aging Issue on Unconnected/Used GTS Input Reference Clock Pins). The recommended recovery sequence is to hold TX and RX PMA reset while the clock is absent, restore the clock, release the resets, request buffer turn-on, and verify the acknowledge and cleared failure status (GTS TX PLL Lock Status Guidelines). Enabling reference clock buffer recovery logic in the applicable GTS PHY or Ethernet IP exposes status and control ports that allow user logic to automate the recovery sequence (Low Latency 40G Ethernet IP Parameters). Best Wishes BB15Views0likes0CommentsRe: NIOS V/m dbg_reset_out signal (Q25.1 Std, MAX10)
Dear pp123 , I'm glad that your issue is resolved. We will continue to monitor this post for the next 5 days. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions. Thank you for engaging with us! Best regards, Altera Technical Support66Views0likes0CommentsRe: Where is FreeRTOS-Plus-TCP Design
Dear JLee25 , I'm glad that your issue is resolved. We will continue to monitor this post for the next 5 days. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions. Thank you for engaging with us! Best regards, Altera Technical Support80Views0likes0CommentsRe: No Nios II target connection
Dear anonimcs, Since clarification has been provided and no further follow‑up questions have been raised, we will assume the issue has been resolved. This thread will now be transitioned to community support, where other users can continue to assist with any additional inquiries. For new questions, please feel free to open a fresh thread — we’ll be happy to support you there. Thank you for being part of the community! Best regards, Altera Technical Support31Views0likes0CommentsRe: Agilex 5 AI flow
Hi K606, I hope you’re doing well. I wanted to follow up and check if there are any remaining questions or concerns regarding this matter. Please let us know if anything still needs clarification — we’re happy to assist further. Thank you for your time, and we look forward to your feedback. Best Wishes BB26Views0likes0CommentsRe: Access to RLC data for Agilex5 IBIS Models
Hi matp , I hope you’re doing well. I wanted to follow up and check if there are any remaining questions or concerns regarding this matter. Please let us know if anything still needs clarification — we’re happy to assist further. Thank you for your time, and we look forward to your feedback. Best Wishes BB68Views0likes1CommentRe: USING SIGNAL TAP TO MONOTOR AVALON_BUS WITH NIOS DESIGN
Hi aiedb, Greetings, as we do not receive any further clarification/updates on the matter, hence would assume challenge are overcome. We will continue to monitor this post for the next 5 days. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions. Thank you for engaging with us! Best regards, Altera Technical Support34Views0likes0Comments