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BoonBengT_Altera
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Re: [Test only]Cyclone V emmc speed
Please find the below suggested answer: eMMC Version Support The Cyclone V HPS SD/MMC controller supports eMMC with 1-bit, 4-bit, and 8-bit data bus widths, per MMC version 4.41. So your statement that v4.5/v5.0 chips fall back to v4.41 constraints is correct. DDR Mode DDR mode is not supported — this applies to both MMC version 4.41 and eMMC. Your SDR-only characterization is accurate. Maximum Clock Speed and Throughput The MMC Support Matrix confirms eMMC has a maximum clock speed of 50 MHz and a maximum data rate of 50 MB/s. Your theoretical ceiling of 50 MB/s (50 MHz × 8-bit SDR) is consistent with this. The practical read/write figures you cite (40–45 MB/s read, 20–25 MB/s write) are reasonable real-world estimates, though those specific numbers aren't stated in the documentation — label them as empirical observations rather than documented specs. One correction: HS200 and controller vintage Your third bullet ("the controller was designed before HS200 existed") is directionally correct but goes beyond what the documentation explicitly states. What the docs do confirm is that the SD/MMC controller is based on the Synopsys DesignWare Mobile Storage Host controller, and the documented maximum is 50 MHz / 50 MB/s SDR. I'd avoid asserting the HS200 non-support as a "controller vintage" argument — just state the documented ceiling directly. Voltage Switching Note One thing worth adding for completeness: the SD/MMC controller does not directly support voltage switching, card interrupts, or back-end power control of eSDIO card devices — however, those signals can be connected to GPIOs. This is relevant if your eMMC chip expects 1.8 V signaling for higher-speed modes. Reset Consideration Also worth noting for robustness: it is required to reset the QSPI and SD/MMC/eMMC boot flash devices each time there is an HPS reset (warm or cold). The SD/MMC controller does not contain a reset output as part of the external card interface, so consider using a general purpose output pin for this. Bottom line: your analysis is solid. The 50 MB/s theoretical / ~45 MB/s practical read ceiling is well-supported by the documented specs, and the SDR-only, 50 MHz max characterization is accurate. Sources: Features of the SD/MMC Controller, SD/MMC Controller, MMC Support Matrix, SD/MMC Controller Block Diagram and System Integration, Cyclone V · HPS/Embedded8Views0likes0CommentsRe: NIOS V/m dbg_reset_out signal (Q25.1 Std, MAX10)
Dear pp123 , I'm glad that your issue is resolved. We will continue to monitor this post for the next 5 days. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions. Thank you for engaging with us! Best regards, Altera Technical Support52Views0likes0CommentsRe: Where is FreeRTOS-Plus-TCP Design
Dear JLee25 , I'm glad that your issue is resolved. We will continue to monitor this post for the next 5 days. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions. Thank you for engaging with us! Best regards, Altera Technical Support66Views0likes0CommentsRe: No Nios II target connection
Dear anonimcs, Since clarification has been provided and no further follow‑up questions have been raised, we will assume the issue has been resolved. This thread will now be transitioned to community support, where other users can continue to assist with any additional inquiries. For new questions, please feel free to open a fresh thread — we’ll be happy to support you there. Thank you for being part of the community! Best regards, Altera Technical Support25Views0likes0CommentsRe: Agilex 5 AI flow
Hi K606, I hope you’re doing well. I wanted to follow up and check if there are any remaining questions or concerns regarding this matter. Please let us know if anything still needs clarification — we’re happy to assist further. Thank you for your time, and we look forward to your feedback. Best Wishes BB20Views0likes0CommentsRe: Access to RLC data for Agilex5 IBIS Models
Hi matp , I hope you’re doing well. I wanted to follow up and check if there are any remaining questions or concerns regarding this matter. Please let us know if anything still needs clarification — we’re happy to assist further. Thank you for your time, and we look forward to your feedback. Best Wishes BB47Views0likes1CommentRe: USING SIGNAL TAP TO MONOTOR AVALON_BUS WITH NIOS DESIGN
Hi aiedb, Greetings, as we do not receive any further clarification/updates on the matter, hence would assume challenge are overcome. We will continue to monitor this post for the next 5 days. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions. Thank you for engaging with us! Best regards, Altera Technical Support25Views0likes0Comments