Video Processing using Altera Quartus 2

I suspect the first one wasnt connected properly and most of the logic removed.

Why not post some code so we can review it?

Here is my code, my x1 module: I only put entity and componenets since the window signal is 7*7 std_logic_vector array and all its components are multiplied and then the results are passed to parallel adder(49 words).

entity x1 is

port(

clk : in std_logic;

window : in Windows;

result_sig : out std_LOGIC_VECTOR(29 downto 0)

 );

end x1;

architecture Behavioral of x1 is

component mult

PORT

(

dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

datab : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

result : OUT STD_LOGIC_VECTOR (23 DOWNTO 0)

 );

END component;

component addmult

PORT

(

data0x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data10x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data11x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data12x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data13x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data14x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data15x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data16x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data17x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data18x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data19x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data1x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data20x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data21x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data22x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data23x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data24x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data25x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data26x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data27x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data28x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data29x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data2x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data30x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data31x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data32x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data33x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data34x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data35x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data36x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data37x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data38x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data39x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data3x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data40x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data41x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data42x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data43x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data44x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data45x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data46x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data47x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data48x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data4x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data5x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data6x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data7x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data8x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data9x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

result : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)

 );

END component;

this x1 module is used as a component in top module and the window signal is passed to x1 from the following process :

process(clk)

begin

if(rising_edge(clk)) then

if(startWindowing="11") then

if(xIterator>2 and xIterator<1387 and yIterator>2 and yIterator<897) then

window(0)<=(line1(xIterator-3),line1(xIterator-2),line1(xIterator-1),line1(xIterator),line1(xIterator+1),line1(xIterator+2),line1(xIterator+3));

window(1)<=(line2(xIterator-3),line2(xIterator-2),line2(xIterator-1),line2(xIterator),line2(xIterator+1),line2(xIterator+2),line2(xIterator+3));

window(2)<=(line3(xIterator-3),line3(xIterator-2),line3(xIterator-1),line3(xIterator),line3(xIterator+1),line3(xIterator+2),line3(xIterator+3));

window(3)<=(line4(xIterator-3),line4(xIterator-2),line4(xIterator-1),line4(xIterator),line4(xIterator+1),line4(xIterator+2),line4(xIterator+3));

window(4)<=(line5(xIterator-3),line5(xIterator-2),line5(xIterator-1),line5(xIterator),line5(xIterator+1),line5(xIterator+2),line5(xIterator+3));

window(5)<=(line6(xIterator-3),line6(xIterator-2),line6(xIterator-1),line6(xIterator),line6(xIterator+1),line6(xIterator+2),line6(xIterator+3));

window(6)<=(line7(xIterator-3),line7(xIterator-2),line7(xIterator-1),line7(xIterator),line7(xIterator+1),line7(xIterator+2),line7(xIterator+3));

end if;

xIterator<=xIterator+1;

if(xIterator=1440) then

xIterator<=0;

yIterator<=yIterator+1;

if(yIterator=900) then

yIterator<=0;

end if;

end if;

end if;

end if;

end process;

Thanks for the replies, I really appriciate your helps

This doesnt really tell us anything. You need to post the whole code.

Do you see any warnings about logic removal? Have you got a pinout for the top level?

library IEEE;

use IEEE.numeric_std.all;

use IEEE.STD_LOGIC_1164.ALL;

library work;

use work.CustomTypes.all;

entity x1 is

port(

clk : in std_logic;

window : in Windows;

result_sig : out std_LOGIC_VECTOR(29 downto 0)

);

end x1;

architecture Behavioral of x1 is

component mult

PORT

(

dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

datab : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

result : OUT STD_LOGIC_VECTOR (23 DOWNTO 0)

);

END component;

component addmult

PORT

(

data0x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data10x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data11x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data12x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

.

.

.

data46x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data47x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data48x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data4x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data5x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data6x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data7x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data8x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data9x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

result : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)

);

END component;

signal dataa_sig : std_LOGIC_VECTOR(7 downto 0);

signal datab_sig : std_LOGIC_VECTOR(15 downto 0);

signal dataa_sig1 : std_LOGIC_VECTOR(7 downto 0);

signal datab_sig1 : std_LOGIC_VECTOR(15 downto 0);

signal dataa_sig2 : std_LOGIC_VECTOR(7 downto 0);

signal datab_sig2 : std_LOGIC_VECTOR(15 downto 0);

signal dataa_sig3 : std_LOGIC_VECTOR(7 downto 0);

signal datab_sig3 : std_LOGIC_VECTOR(15 downto 0);

.

.

.

signal dataa_sig47 : std_LOGIC_VECTOR(7 downto 0);

signal datab_sig47 : std_LOGIC_VECTOR(15 downto 0);

signal dataa_sig48 : std_LOGIC_VECTOR(7 downto 0);

signal datab_sig48 : std_LOGIC_VECTOR(15 downto 0);

--signal result_sig : std_LOGIC_VECTOR(23 downto 0);

signal data0x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data10x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data11x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data12x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data13x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data14x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data15x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data16x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data17x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data18x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data19x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data1x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data20x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data21x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data22x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data23x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data24x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data25x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data26x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data27x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data28x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data29x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data2x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data30x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data31x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data32x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data33x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data34x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data35x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data36x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data37x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data38x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data39x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data3x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data40x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data41x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data42x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data43x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data44x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data45x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data46x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data47x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data48x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data4x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data5x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data6x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data7x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data8x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data9x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

begin

mult_inst : mult PORT MAP (

dataa => window(0)(0),

datab => datab_sig,

result => data0x_sig

);

mult_inst1 : mult PORT MAP (

dataa => window(0)(1),

datab => datab_sig1,

result => data10x_sig

);

mult_inst2 : mult PORT MAP (

dataa => window(0)(2),

datab => datab_sig2,

result => data11x_sig

);

this continues up to window(7)(7)

continues as follows:

addmult_inst : addmult PORT MAP (

data0x => data0x_sig,

data10x => data10x_sig,

data11x => data11x_sig,

data12x => data12x_sig,

data13x => data13x_sig,

data14x => data14x_sig,

data15x => data15x_sig,

data16x => data16x_sig,

data17x => data17x_sig,

data18x => data18x_sig,

data19x => data19x_sig,

data1x => data1x_sig,

data20x => data20x_sig,

data21x => data21x_sig,

data22x => data22x_sig,

data23x => data23x_sig,

data24x => data24x_sig,

data25x => data25x_sig,

data26x => data26x_sig,

data27x => data27x_sig,

data28x => data28x_sig,

data29x => data29x_sig,

data2x => data2x_sig,

data30x => data30x_sig,

data31x => data31x_sig,

data32x => data32x_sig,

data33x => data33x_sig,

data34x => data34x_sig,

data35x => data35x_sig,

data36x => data36x_sig,

data37x => data37x_sig,

data38x => data38x_sig,

data39x => data39x_sig,

data3x => data3x_sig,

data40x => data40x_sig,

data41x => data41x_sig,

data42x => data42x_sig,

data43x => data43x_sig,

data44x => data44x_sig,

data45x => data45x_sig,

data46x => data46x_sig,

data47x => data47x_sig,

data48x => data48x_sig,

data4x => data4x_sig,

data5x => data5x_sig,

data6x => data6x_sig,

data7x => data7x_sig,

data8x => data8x_sig,

data9x => data9x_sig,

result => result_sig

);

datab_sig<="0000000010010011";

datab_sig1<="0000000010010011";

datab_sig2<="0000000010010011";

datab_sig3<="0000000010010011";

datab_sig4<="0000000010010011";

datab_sig5<="0000000010010011";

datab_sig6<="0000000010010011";

datab_sig7<="0000000010010011";

datab_sig8<="0000000010010011";

datab_sig9<="0000000010010011";

datab_sig10<="0000000010010011";

datab_sig11<="0000000010010011";

datab_sig12<="0000000010010011";

datab_sig13<="0000000010010011";

datab_sig14<="0000000010010011";

datab_sig15<="0000000010010011";

datab_sig16<="0000000010010011";

datab_sig17<="0000000010010011";

datab_sig18<="0000000010010011";

datab_sig19<="0000000010010011";

datab_sig20<="0000000010010011";

datab_sig21<="0000000010010011";

datab_sig22<="0000000010010011";

datab_sig23<="0000000010010011";

datab_sig24<="0000000010010011";

datab_sig25<="0000000010010011";

datab_sig26<="0000000010010011";

datab_sig27<="0000000010010011";

datab_sig28<="0000000010010011";

datab_sig29<="0000000010010011";

datab_sig30<="0000000010010011";

datab_sig31<="0000000010010011";

datab_sig32<="0000000010010011";

datab_sig33<="0000000010010011";

datab_sig34<="0000000010010011";

datab_sig35<="0000000010010011";

datab_sig36<="0000000010010011";

datab_sig37<="0000000010010011";

datab_sig38<="0000000010010011";

datab_sig39<="0000000010010011";

datab_sig40<="0000000010010011";

datab_sig41<="0000000010010011";

datab_sig42<="0000000010010011";

datab_sig43<="0000000010010011";

datab_sig44<="0000000010010011";

datab_sig45<="0000000010010011";

datab_sig46<="0000000010010011";

datab_sig47<="0000000010010011";

datab_sig48<="0000000010010011";

end Behavioral

top module:

library IEEE;

use IEEE.numeric_std.all;

use IEEE.STD_LOGIC_1164.ALL;

use work.CustomTypes.all;

entity FrameSelector is

port(

clk : in std_logic;

redin : in std_logic_vector(7 downto 0);

result_sig : out std_LOGIC_VECTOR(29 downto 0)

--window : out windows

);

end FrameSelector;

architecture Behavioral of FrameSelector is

--type WindowLine is array (6 downto 0) of std_logic_vector(7 downto 0);

--type PixelLine is array (1439 downto 0) of std_logic_vector(7 downto 0);

--type Windows is array (6 downto 0) of WindowLine;

Signal window,windowtemp : Windows;

signal line1,line2,line3,line4,line5,line6,line7,linetemp : PixelLine;

signal StartWindowing : std_LOGIC_VECTOR(1 downto 0):="00";

signal xIterator : integer range 0 to 1439:=0;

signal yIterator : integer range 0 to 899:=0;

component x1

port(

clk : in std_logic;

window : in Windows;

result_sig : out std_LOGIC_VECTOR(29 downto 0)

);

end component;

begin

conv2d : deneme

port map(

clk=>clk,

window=>windowtemp,

result_sig=>result_sig

);

windowtemp<=window;

-------------------Line saving Process----------------------------------

process(clk)

variable xpos : integer:=0;

variable ypos : integer:=0;

begin

if(rising_edge(clk)) then

linetemp(xpos)<=redin;

xpos:=xpos+1;

if(xpos=1440) then

ypos:=ypos+1;

xpos:=0;

if(ypos=1) then

line1<=linetemp;

elsif(ypos=2) then

line2<=linetemp;

elsif(ypos=3) then

line3<=linetemp;

elsif(ypos=4) then

line4<=linetemp;

startWindowing<="11";

elsif(ypos=5) then

line5<=linetemp;

elsif(ypos=6) then

line6<=linetemp;

elsif(ypos=7) then

line7<=linetemp;

else

line1<=line2;

line2<=line3;

line3<=line4;

line4<=line5;

line5<=line6;

line6<=line7;

line7<=linetemp;

end if;

if(ypos=900) then

ypos:=0;

end if;

end if;

end if;

end process;

--------------------Windowing Processs------------------------------------

process(clk)

begin

if(rising_edge(clk)) then

if(startWindowing="11") then

lot of if else statements about xpos and ypos

end if;

xIterator<=xIterator+1;

if(xIterator=1440) then

xIterator<=0;

yIterator<=yIterator+1;

if(yIterator=900) then

yIterator<=0;

end if;

end if;

end if;

end if;

end process;

end Behavioral;

no logic removal or any other warnings...

Have you simulated the design?

can you post up the quartus project as a .qar file?

Ok.

So, the fact it uses 1% means something (or most of the design) is removed. I expect this design to use most of the chip, if it actually synthesises to anything, as you havent used any rams - all your "lines" will be stored as registers.

Also - this code is terrible - I have no real idea whats going on. Theres a load of multipliers and some windowing along a load of registers. Where is the source of the data? Is it really just a counter?

And where is the testbench?

This doesnt look like a serious design - no inputs and no outputs.