Video Processing using Altera Quartus 2

library IEEE;

use IEEE.numeric_std.all;

use IEEE.STD_LOGIC_1164.ALL;

library work;

use work.CustomTypes.all;

entity x1 is

port(

clk : in std_logic;

window : in Windows;

result_sig : out std_LOGIC_VECTOR(29 downto 0)

);

end x1;

architecture Behavioral of x1 is

component mult

PORT

(

dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

datab : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

result : OUT STD_LOGIC_VECTOR (23 DOWNTO 0)

);

END component;

component addmult

PORT

(

data0x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data10x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data11x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data12x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

.

.

.

data46x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data47x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data48x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data4x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data5x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data6x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data7x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data8x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data9x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

result : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)

);

END component;

signal dataa_sig : std_LOGIC_VECTOR(7 downto 0);

signal datab_sig : std_LOGIC_VECTOR(15 downto 0);

signal dataa_sig1 : std_LOGIC_VECTOR(7 downto 0);

signal datab_sig1 : std_LOGIC_VECTOR(15 downto 0);

signal dataa_sig2 : std_LOGIC_VECTOR(7 downto 0);

signal datab_sig2 : std_LOGIC_VECTOR(15 downto 0);

signal dataa_sig3 : std_LOGIC_VECTOR(7 downto 0);

signal datab_sig3 : std_LOGIC_VECTOR(15 downto 0);

.

.

.

signal dataa_sig47 : std_LOGIC_VECTOR(7 downto 0);

signal datab_sig47 : std_LOGIC_VECTOR(15 downto 0);

signal dataa_sig48 : std_LOGIC_VECTOR(7 downto 0);

signal datab_sig48 : std_LOGIC_VECTOR(15 downto 0);

--signal result_sig : std_LOGIC_VECTOR(23 downto 0);

signal data0x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data10x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data11x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data12x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data13x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data14x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data15x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data16x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data17x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data18x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data19x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data1x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data20x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data21x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data22x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data23x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data24x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data25x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data26x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data27x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data28x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data29x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data2x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data30x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data31x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data32x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data33x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data34x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data35x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data36x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data37x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data38x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data39x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data3x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data40x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data41x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data42x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data43x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data44x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data45x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data46x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data47x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data48x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data4x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data5x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data6x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data7x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data8x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

signal data9x_sig : STD_LOGIC_VECTOR (23 DOWNTO 0);

begin

mult_inst : mult PORT MAP (

dataa => window(0)(0),

datab => datab_sig,

result => data0x_sig

);

mult_inst1 : mult PORT MAP (

dataa => window(0)(1),

datab => datab_sig1,

result => data10x_sig

);

mult_inst2 : mult PORT MAP (

dataa => window(0)(2),

datab => datab_sig2,

result => data11x_sig

);

this continues up to window(7)(7)