Video Processing using Altera Quartus 2

Here is my code, my x1 module: I only put entity and componenets since the window signal is 7*7 std_logic_vector array and all its components are multiplied and then the results are passed to parallel adder(49 words).

entity x1 is

port(

clk : in std_logic;

window : in Windows;

result_sig : out std_LOGIC_VECTOR(29 downto 0)

 );

end x1;

architecture Behavioral of x1 is

component mult

PORT

(

dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

datab : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

result : OUT STD_LOGIC_VECTOR (23 DOWNTO 0)

 );

END component;

component addmult

PORT

(

data0x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data10x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data11x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data12x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data13x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data14x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data15x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data16x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data17x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data18x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data19x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data1x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data20x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data21x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data22x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data23x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data24x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data25x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data26x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data27x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data28x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data29x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data2x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data30x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data31x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data32x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data33x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data34x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data35x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data36x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data37x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data38x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data39x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data3x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data40x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data41x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data42x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data43x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data44x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data45x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data46x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data47x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data48x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data4x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data5x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data6x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data7x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data8x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

data9x : IN STD_LOGIC_VECTOR (23 DOWNTO 0);

result : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)

 );

END component;

this x1 module is used as a component in top module and the window signal is passed to x1 from the following process :

process(clk)

begin

if(rising_edge(clk)) then

if(startWindowing="11") then

if(xIterator>2 and xIterator<1387 and yIterator>2 and yIterator<897) then

window(0)<=(line1(xIterator-3),line1(xIterator-2),line1(xIterator-1),line1(xIterator),line1(xIterator+1),line1(xIterator+2),line1(xIterator+3));

window(1)<=(line2(xIterator-3),line2(xIterator-2),line2(xIterator-1),line2(xIterator),line2(xIterator+1),line2(xIterator+2),line2(xIterator+3));

window(2)<=(line3(xIterator-3),line3(xIterator-2),line3(xIterator-1),line3(xIterator),line3(xIterator+1),line3(xIterator+2),line3(xIterator+3));

window(3)<=(line4(xIterator-3),line4(xIterator-2),line4(xIterator-1),line4(xIterator),line4(xIterator+1),line4(xIterator+2),line4(xIterator+3));

window(4)<=(line5(xIterator-3),line5(xIterator-2),line5(xIterator-1),line5(xIterator),line5(xIterator+1),line5(xIterator+2),line5(xIterator+3));

window(5)<=(line6(xIterator-3),line6(xIterator-2),line6(xIterator-1),line6(xIterator),line6(xIterator+1),line6(xIterator+2),line6(xIterator+3));

window(6)<=(line7(xIterator-3),line7(xIterator-2),line7(xIterator-1),line7(xIterator),line7(xIterator+1),line7(xIterator+2),line7(xIterator+3));

end if;

xIterator<=xIterator+1;

if(xIterator=1440) then

xIterator<=0;

yIterator<=yIterator+1;

if(yIterator=900) then

yIterator<=0;

end if;

end if;

end if;

end if;

end process;

Thanks for the replies, I really appriciate your helps