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Altera_Forum's avatar
Altera_Forum
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9 years ago

VHDL syntax error ---- parser stack overf

Hallo

I am trying to use the FIR Interpolation Block from Simulink with 4096 coefficients and 256 upsampling. I using the hdl coder to generate the VHDL code and then Altera Quatrus 2 to synthesize the code. My HDL code generates perfectly. But when i try to synthesize it i run in to the following error

VHDL syntax error at FIR_Interpolation.vhd(11060) near text "2495"parser stack overflow FIR_Interpolation.vhd Line: 11060

I am attaching the VHDL file that i am generating.

Is it like i have too many filter coefficients? I am able to synthesize the filter with 512 coefficients set and 32 bit upsample. Then i tried the same filter with this setting and i get this error. Can anyone help me with the error?

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    That is a large file - and looks like a compiler crash

    What version of Quartus is it? have you tried using a newer version?

    Otherwise, you'll need to raise a support request with altera via MySupport on their website.

    Have you tried simulating the design?
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Hallo

    thanks for the quick reply

    This is MATLAB 2014b, Altera Quatras 2 (version 13.0 web edition). I tried using version 16.1 but it was not supported for my MATLAB version. If you think upgrading the version would help i can try upgrading my MATLAB and Altera version.

    Yes the design simulates in simulink perfectly. What did you exactly mean by simulating the design?
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    The version of quartus should not matter - all you are passing to Quartus is HDL code. So you should be able to try the new version without having to set anything in simulink.

    Simulation is done in an HDL simulator like Modelsim (you get a free version from altera too). This simulates the HDL (and will be another compiler check)

    But the original error looks like a quartus crash. hence the suggestion to try a newer version of Quartus.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Such a large FIR Filter though is likely to run very very very slow on an FPGA - it's trying to mux between 4096 32 bit values - I suspect the FMax is not going to be more than a few MHz.

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    I don't think that the free modelsim will work with such a large file.

    Just curious, what needs a filter with such a huge number of coefficients?