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Altera_Forum
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9 years ago

VHDL syntax error ---- parser stack overf

Hallo I am trying to use the FIR Interpolation Block from Simulink with 4096 coefficients and 256 upsampling. I using the hdl coder to generate the VHDL code and then Altera Quatrus 2 to synthe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

That is a large file - and looks like a compiler crash

What version of Quartus is it? have you tried using a newer version?

Otherwise, you'll need to raise a support request with altera via MySupport on their website.

Have you tried simulating the design?