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Altera_Forum
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9 years ago

VHDL syntax error ---- parser stack overf

Hallo I am trying to use the FIR Interpolation Block from Simulink with 4096 coefficients and 256 upsampling. I using the hdl coder to generate the VHDL code and then Altera Quatrus 2 to synthe...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Hallo

thanks for the quick reply

This is MATLAB 2014b, Altera Quatras 2 (version 13.0 web edition). I tried using version 16.1 but it was not supported for my MATLAB version. If you think upgrading the version would help i can try upgrading my MATLAB and Altera version.

Yes the design simulates in simulink perfectly. What did you exactly mean by simulating the design?