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Honored Contributor
Honored ContributorVHDL syntax error ---- parser stack overf
Hallo I am trying to use the FIR Interpolation Block from Simulink with 4096 coefficients and 256 upsampling. I using the hdl coder to generate the VHDL code and then Altera Quatrus 2 to synthe...
Altera_ForumHonored Contributor
Honored ContributorSuch a large FIR Filter though is likely to run very very very slow on an FPGA - it's trying to mux between 4096 32 bit values - I suspect the FMax is not going to be more than a few MHz.
