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Altera_Forum
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9 years ago

VHDL syntax error ---- parser stack overf

Hallo I am trying to use the FIR Interpolation Block from Simulink with 4096 coefficients and 256 upsampling. I using the hdl coder to generate the VHDL code and then Altera Quatrus 2 to synthe...
Altera_Forum's avatar
Altera_Forum
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9 years ago

The version of quartus should not matter - all you are passing to Quartus is HDL code. So you should be able to try the new version without having to set anything in simulink.

Simulation is done in an HDL simulator like Modelsim (you get a free version from altera too). This simulates the HDL (and will be another compiler check)

But the original error looks like a quartus crash. hence the suggestion to try a newer version of Quartus.