New Contributorvhdl signal delay block code randomly not working
Hello,
I'm trying to run a signal delay block I coded in VHDL on an Altera MAX II. It works "normally" but sometimes it seems it doesn't apply the delay as expexted. Do you have any idea of what I did wrong?
Thanks
Michele
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.Numeric_std.all;
ENTITY Delay IS
PORT
(
input : IN std_logic;
delayType : IN std_logic;
clk : IN std_logic;
output : OUT std_logic
);
END Delay;
ARCHITECTURE Delay_signals OF Delay IS
signal output_status : std_logic;
signal status_counter : std_logic_vector(7 downto 0);
signal counter_thr: std_logic_vector(7 downto 0);
BEGIN
PROCESS (clk, input, delayType, output_status)
BEGIN
IF delayType = '0' THEN
-- GateDelay for external 2 us = 80 ticks
counter_thr <= B"01010000";
ELSE
-- Internal IGBTs delay 3.5 us = 140 ticks
counter_thr <= B"10001100";
END IF;
IF rising_edge(clk) THEN
IF input = '1' THEN
IF output_status = '0' THEN
status_counter <= status_counter + 1;
-- 1 us = 40 ticks
IF status_counter > counter_thr THEN
output_status <= '1';
status_counter <= (others => '0');
END IF;
ELSE
status_counter <= (others => '0');
END IF;
ELSE
IF output_status = '1' THEN
status_counter <= status_counter + 1;
IF status_counter > counter_thr THEN
output_status <= '0';
status_counter <= (others => '0');
END IF;
ELSE
status_counter <= (others => '0');
END IF;
END IF;
END IF;
output <= output_status;
END PROCESS;
END Delay_signals;
