vhdl signal delay block code randomly not working

​Hi,

I didn't write the testbench. I'm using the MAX II to route some signals using a main schematic file, .bdf, where I do some AND&OR logics: it's a 10 years old design. I recently tried to add some delays with the code I posted and I noticed that normally the input signal is correctly delayed with the forecasted value: it just randomly cuts the delay at the rise or fall. It seems like my "static variable" output_status sometimes doesn't retain the correct value more than a clock issue because otherwise I would expect to experience some random effects also on the value of the delay applied instead or the delay is right there (most of the times) or it's cut.

Maybe it's worth to say that I'm using this block multiple times in the schematic

thanks for your support.

Regards

Michele