Forum Discussion
mcorr16
New Contributor
6 years agoHello,
yes I solved the issue. It was not linked to my VHDL design but to metastability problem
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01082-quartus-ii-metastability.pdf
Passing all my inputs through a flip-flop solved I the problem.
thanks
regards
Michele