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mcorr16's avatar
mcorr16
Icon for New Contributor rankNew Contributor
6 years ago

vhdl signal delay block code randomly not working

Hello, I'm trying to run a signal delay block I coded in VHDL on an Altera MAX II. It works "normally" but sometimes it seems it doesn't apply the delay as expexted. Do you have any idea of what I d...
Vicky1's avatar
Vicky1
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Michele,

"Hi,

Have you verified the functionality of your design by writing the testbench?

Please share here simulation screenshot & elaborate your observation.

Regards,

Vicky" --------- I would like to suggest before implementing any design(HDL or schematic) on board you should verify the functionality of the design writing testbench & tracing the simulation waveforms so if you want to clarify your issue, please provide screenshot of your simulation window.

Regards,

Vicky