Altera_Forum
Honored Contributor
Honored ContributorVHDL mod operator
Thank you. problem solved
Forum Discussion
11 Replies
Altera_Forum--- Quote Start --- but getting error in the last step --- Quote End --- Means what? The missing end statement? Despite of the confuse type mix, the code compiles well in Quartus.- Altera_Forum
Hi, first of all, delete
They are not compatible with "numeric_std" Second, you can't convert integer to std_logic_vector directly, you need Integer---> Signed/unsigned---->std_logic_vector. But I can't see where you are wrong in conversions, maube the MOD function. Pdt2_int should be 11-bit wide be careful using process like this, you will create latch and unexpected results. You should give all signal that enters the process in the sensitivity list. and Why are you using a process ? I think "(integer) MOD (integer)" doesn't work. It would be "(signed) MOD (integer)" or "(integer) MOD (signed)"USE ieee.std_logic_signed.ALL; USE ieee.std_logic_unsigned.ALL; - Altera_Forum--- Quote Start --- Hi, first of all, delete
They are not compatible with "numeric_std" --- Quote End --- They are perfectly compatible with numeric_std. They just arent compatible with each other, you should only use 1 at a time (not both). numeric_std only conflicts with std_logic_arith. --- Quote Start --- Second, you can't convert integer to std_logic_vector directly, you need Integer---> Signed/unsigned---->std_logic_vector. But I can't see where you are wrong in conversions, maube the MOD function. --- Quote End --- There is no std_logic_vector->integer conversion in the OPs code. --- Quote Start --- be careful using process like this, you will create latch and unexpected results. You should give all signal that enters the process in the sensitivity list. --- Quote End --- No Latches will be created because there are no conditional branches - it is a purely combinatorial process. The signals are missing from the sensitivity list though, but that means simulation behaviour will not match the hardware. Synthesis ignores sensitivity lists.USE ieee.std_logic_signed.ALL; USE ieee.std_logic_unsigned.ALL; - Altera_Forum
OK Tricky for corrections,
but you said "Synthesis simply ignores sensitivity lists", sure ? So how D flip flop are created ? @ varun_v16 : what error message did you get ? - Altera_Forum
yes sensitity lists are completly ignored. It uses code templates to recognise flip flops. Anything inside a rising_edge(clk) area will be treated as a register. as will this code (which has no sensitivty list:
if your assumption about senstivity lists were correct, then the following code would create a flip flop, but it does not:process begin wait until clk = '1'; --this area will generate a DFF in Quartus end processprocess(clk) begin if clk = '1' then --this will NOT create a register in Quartus, but it will look like one in simulation end if; end process - Altera_Forum
I don't use wait statement, so I believe you.
To come back to this thread, I think varun_v16 got an error at the "mod" function. See also : http://www.doulos.com/knowhow/vhdl_designers_guide/numeric_std/ Regards - Altera_Forum
z, d_int and a are all integers. Mod is defined for integers. Hence no problem.
We're waiting for the OP to reply with what the error is. - Altera_Forum
I got all the errors fixed now. Just wanted to make sure that the logic and conversions were right and were legal but thank you. Life savers if I may exaggerate
- Altera_Forum
Glad you got the errors fixed. Given the code has no clock, and the use of the mod operator, I assume the data rate is extremely slow.
- Altera_Forum
And its very rude to delete your origional post
