VHDL mod operator

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Hi, first of all, delete

USE ieee.std_logic_signed.ALL;
USE ieee.std_logic_unsigned.ALL;

They are not compatible with "numeric_std"

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They are perfectly compatible with numeric_std. They just arent compatible with each other, you should only use 1 at a time (not both).

numeric_std only conflicts with std_logic_arith.

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Second, you can't convert integer to std_logic_vector directly, you need Integer---> Signed/unsigned---->std_logic_vector. But I can't see where you are wrong in conversions, maube the MOD function.

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There is no std_logic_vector->integer conversion in the OPs code.

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be careful using process like this, you will create latch and unexpected results. You should give all signal that enters the process in the sensitivity list.

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No Latches will be created because there are no conditional branches - it is a purely combinatorial process. The signals are missing from the sensitivity list though, but that means simulation behaviour will not match the hardware. Synthesis ignores sensitivity lists.