VHDL mod operator

yes sensitity lists are completly ignored. It uses code templates to recognise flip flops. Anything inside a rising_edge(clk) area will be treated as a register. as will this code (which has no sensitivty list:

process
begin
  wait until clk = '1';
  
  --this area will generate a DFF in Quartus
end process

if your assumption about senstivity lists were correct, then the following code would create a flip flop, but it does not:

process(clk)
begin
  if clk = '1' then
    --this will NOT create a register in Quartus, but it will look like one in simulation
  end if;
end process