We tried to do a very simple thing: a demultiplexer that enables one of several gates according to the state of an n-signal vector. (Just static, no Flipflops involved.) So we defined a 2^n signal vector and set the default value to "0" and later in the code we set one of it's the signals to "1" by an appropriate statement. We were used to use this method with Xilinx projects and it did work fine there. We did find a (supposedly more "recommended") way to create a demultiplexer (without using default values), so no harm done, but.... Our first try might be considered "bad style" but the Quartus did not complain and I don't see why this does not work with Quartus (but with teh Xilinx tool chain). So I feel this is might be a bug.... -Michael

Please post the code, as it will make alot more sense than your explanation.

You also didn't mention what's the unexpected behaviour. Usually, similar issues turn out as strictly correct operation related to the respective HDL specification.

This did not work (seemingly load(i) always was 0 in some or all cases ): signal load: std_logic_vector (63 downto 0) := (others => '0'); ... load(conv_integer(address)) <= '1'; ... < now we use load(...) > ... This did work: signal load: std_logic_vector (63 downto 0); ... G1: for i in 0 to 63 generate begin load(i) <= '1' when (conv_integer(address) = i) else '0'; end generate G1 ... < now we use load(...) > ... -Michael

From looking at the code you have posted, they are not the same thing. The second example sets every bit to '0', and the selected address to '1' every time the address changes. The first (non working) example is making latches. You may be inititialising all the results to '0' but you are latching a '1' into them when the address is set, and then they will stay at '1' for ever.

Oops (maybe this is a silly question, as I am new to VHDL, while the colleage of mine who does work with VHDL since some time, is not available right now. And of course this is strictly of-topic,so feel free to ignore). >>"The second example sets every bit to '0'," When ? (My thinking was, "always, unless something else is stated", thus not time-depending but just as logical result of all lines in the module.) What exactly makes the compiler think that I want to store something with the first code and thus it needs to implement any FlipFlops, and not just logic gates ? (No clock is mentioned anywhere, RS-FF with just a set and no reset does not seem to make any sense.) Is it just because there is not "else" ? If we want to do a "synchronous" design (state changes only due to clock edges), how to make sure that no "parasitic" R/S FFs are created ? -Michael

VHDL default signal state bug ? | Altera Community

15 Replies

Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
this second method has no meaning, because you cannot xor an integer with anything, or invert it, or assing it directly to a std_logic_vector.
--- Quote End ---

Oops, no simple operations creating logical results from numerical values ?!?!?!

But if you cay a process does not harm, I do see how to proceed.

Thanks a lot for the VHDL introduction !!!

Michael (having noticed that C is a straight forward language :) )
Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
Oops, no simple operations creating logical results from numerical values ?!?!?!

--- Quote End ---

VHDL is strongly typed, so you have to be careful with your typecasting. an integer is not a collection of bits, so you cant extract them from it. A std_logic_vector is NOT an integer, it is a collection of bits, and can represent anything (an unsigned integer, signed integer, float, double, a bus full of control bits, fixed point binary, BCD - anything). But if you mean to store something as an integer, use an integer type rather than a std_logic_vector.

I notice you use the std_logic_arith/unsigned packages. You might want to change over to iee.numeric_std instead seeing as you are a beginner - best to get into good habits now. Numeric_std is an ieee standard, std_logic_arith and the like are not - they encourage you to forget about the typing that VHDL provides and use std_logic_vectors as integers, which they are not!
Altera_Forum
Honored Contributor
16 years ago
Tricky, Thanks a lot for your help !!!
-Michael
Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
Numeric_std is an ieee standard, std_logic_arith and the like are not
--- Quote End ---

std_logic_arith is the old IEEE standard, still used in all Altera IP till now. It doesn't involve std_logic_unsigned/signed, which is a different thing. Regarding the original question, if you are intending just a simple combinational decoder, the generate variant is a straightforward way to build it.
Altera_Forum
Honored Contributor
16 years ago
std_logic_arith was never an IEEE standard. It was created by synopsys to bring together what everyone else had done in their own packages. Because numeric std wasnt around until vhdl '93 everyone adopted it.

VHDL '08 brings std_logic_arith packages all together again into IEEE standard packages.

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VHDL default signal state bug ?

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