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Oops, no simple operations creating logical results from numerical values ?!?!?!
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VHDL is strongly typed, so you have to be careful with your typecasting. an integer is not a collection of bits, so you cant extract them from it. A std_logic_vector is NOT an integer, it is a collection of bits, and can represent anything (an unsigned integer, signed integer, float, double, a bus full of control bits, fixed point binary, BCD - anything). But if you mean to store something as an integer, use an integer type rather than a std_logic_vector.
I notice you use the std_logic_arith/unsigned packages. You might want to change over to iee.numeric_std instead seeing as you are a beginner - best to get into good habits now. Numeric_std is an ieee standard, std_logic_arith and the like are not - they encourage you to forget about the typing that VHDL provides and use std_logic_vectors as integers, which they are not!
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