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Altera_Forum
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16 years ago

VHDL default signal state bug ?

We tried to do a very simple thing: a demultiplexer that enables one of several gates according to the state of an n-signal vector. (Just static, no Flipflops involved.) So we defined a 2^n sig...
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Altera_Forum
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16 years ago

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Numeric_std is an ieee standard, std_logic_arith and the like are not

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std_logic_arith is the old IEEE standard, still used in all Altera IP till now. It doesn't involve std_logic_unsigned/signed, which is a different thing. Regarding the original question, if you are intending just a simple combinational decoder, the generate variant is a straightforward way to build it.