VHDL: DE2 Lab4 part1

13 Replies

Altera_Forum
Honored Contributor
15 years ago
You have to look at the edge of the clock, not the level.

if (clk = '1') then
become
if rising_edge(Clk) then
About the reset, if it is asynchronous, the first test must be on it and the second on the clock (use if, elsif), else if it is synchronous the first test is on the clock and the second is on the reset.

Honored Contributor

Hmm thanks for the seggestion, but now it does nothing. I guess that takes me to my next question, Is this mess what altera was suggesting by using 16 TFFs to make the counter? :)

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity TFFcounter16bit is
	
	port ( 	enable, clk, rst : in std_logic;
			Qpin	: out unsigned(15 downto 0)
	);
end TFFcounter16bit;
architecture wowee of TFFcounter16bit is
	
	signal Qout : unsigned(15 downto 0);
begin
	
	myTFF0  : entity work.myTFF port map( enable, clk, rst, Qout(0));
	myTFF1  : entity work.myTFF port map( (enable AND Qout(0)), clk, rst, Qout(1));
	myTFF2  : entity work.myTFF port map( ((enable AND Qout(0)) AND Qout(1) ), clk, rst, Qout(2));		
	myTFF3  : entity work.myTFF port map( (((enable AND Qout(0)) AND Qout(1)) AND Qout(2)  ), clk, rst, Qout(3));
	myTFF4  : entity work.myTFF port map( ((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3) ), clk, rst, Qout(4));
	myTFF5  : entity work.myTFF port map( (((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)), clk, rst, Qout(5));
	myTFF6  : entity work.myTFF port map( ((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)), clk, rst, Qout(6));
	myTFF7  : entity work.myTFF port map( (((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)), clk, rst, Qout(7));
	myTFF8  : entity work.myTFF port map( ((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)), clk, rst, Qout(8));
	myTFF9  : entity work.myTFF port map( (((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)) AND Qout(8)), clk, rst, Qout(9));
	myTFF10 : entity work.myTFF port map( ((((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)) AND Qout(8)) AND Qout(9)), clk, rst, Qout(10));
	myTFF11 : entity work.myTFF port map( (((((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)) AND Qout(8)) AND Qout(9)) AND Qout(10)), clk, rst, Qout(11));
	myTFF12 : entity work.myTFF port map( ((((((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)) AND Qout(8)) AND Qout(9)) AND Qout(10)) AND Qout(11)), clk, rst, Qout(12));
	myTFF13 : entity work.myTFF port map( (((((((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)) AND Qout(8)) AND Qout(9)) AND Qout(10)) AND Qout(11)) AND Qout(12)), clk, rst, Qout(13));
	myTFF14 : entity work.myTFF port map( ((((((((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)) AND Qout(8)) AND Qout(9)) AND Qout(10)) AND Qout(11)) AND Qout(12)) AND Qout(13)), clk, rst, Qout(14));
	myTFF15 : entity work.myTFF port map( (((((((((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)) AND Qout(8)) AND Qout(9)) AND Qout(10)) AND Qout(11)) AND Qout(12)) AND Qout(13)) AND Qout(14)), clk, rst, Qout(15));
	
	Qpin <= Qout;
	
end wowee;

Altera_Forum
Honored Contributor
15 years ago
Can you put your modified code of myTFF ?

Altera_Forum

Honored Contributor

15 years ago

sure:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity myTFF is
	port( T, Clk, Reset	: in std_logic;
			Q			: out std_logic
	);
end myTFF;
architecture behavioral of myTFF is
	signal buf : std_logic;
begin
	
	process(T, Clk, Reset)
	begin
	
		if(reset = '1') then
			buf <= '0';
		elsif(rising_edge(Clk))then
			if(T = '1')then
				buf <= (NOT buf);
			end if;
		end if;
	
	end process;
	
	Q <= buf;
	
end behavioral;

Altera_Forum
Honored Contributor
15 years ago
This is correct, except that you don't need to put T signal in the sensitivity list of the process, because the output can change only when the reset is active, or on clock edge.
Altera_Forum
Honored Contributor
15 years ago
ok, but just for the sake of asking, the T being in the sensitivity list wont affect anything will it?

-edit-
And if you're saying that everything looks ok, then there's something wrong with my logic in that scary looking counter. maybe i'll just make a 2-bit one to debug before i move on.
Altera_Forum
Honored Contributor
15 years ago
Put T in the sensitivity list will not change the behaviour, but it is possible that the logic generated be different, I am not sure on it. You can check that with the RTL viewer in Quartus after compilation.

About the counter, there are two things. The first is that I am not sure if you can put equation instead of a signal as a parameter of port map. I would advise to create a signal for inputs of each TFF, and moreover this will simplify the equation. Here you have an example :

signal T : std_logic_vector(16 downto 0); ... T(0) <= enable; T(1) <= Qout(0) & T(0); T(2) <= Qout(1) & T(1); ... myTFFi : entity work.myTFF port map( T(i), clk, rst, Qout(i));
Secondly, you declare Qout as unsigned, whereas output of TFF is std_logic, it is not coherent (Quartus did not give you an error about this ?) You can declare Qout as std_logic_vector, it is not needed to use unsigned since you don't make arithmetic operation on it.
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
Secondly, you declare Qout as unsigned, whereas output of TFF is std_logic, it is not coherent (Quartus did not give you an error about this ?) You can declare Qout as std_logic_vector, it is not needed to use unsigned since you don't make arithmetic operation on it.
--- Quote End ---

Theres nothing wrong with that. Unsigned is an array of std_logic, so Qout(n) is a std_logic.

Altera_Forum

Honored Contributor

15 years ago

I am not totally ok with you. Unsigned is std_logic but with a particular signification. You can assigned an unsigned to a std_logic (I discovered it just now, I did not think that it was possible), but not an unsigned to a std_logic_vector. Here there is an example, with this code :


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Example is
    port
    (
        clock        : in  std_logic;
        reset        : in  std_logic;
        outputScalar : out std_logic;
        outputVector : out std_logic_vector(9 downto 0)
        
    );
end Example;
architecture arch_Example of Example is
signal counter : unsigned(9 downto 0);
begin
    outputVector <= counter;
    outputScalar <= counter(0);
    process(reset, clock)
    begin
        if reset = '1' then
            counter <= (others => '0');
        elsif rising_edge(clock) then
            counter <= counter + 1;
        end if;
    end process;
end architecture arch_Example;

Quartus will give you the following error :

--- Quote Start ---

Error (10476): VHDL error at Example.vhd(22): type of identifier "counter" does not agree with its usage as "std_logic_vector" type

--- Quote End ---

And you have to use the following code


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Example is
    port
    (
        clock        : in  std_logic;
        reset        : in  std_logic;
        outputScalar : out std_logic;
        outputVector : out std_logic_vector(9 downto 0)
        
    );
end Example;
architecture arch_Example of Example is
signal counter : unsigned(9 downto 0);
begin
    outputVector <= std_logic_vector(counter);
    outputScalar <= counter(0);
    process(reset, clock)
    begin
        if reset = '1' then
            counter <= (others => '0');
        elsif rising_edge(clock) then
            counter <= counter + 1;
        end if;
    end process;
end architecture arch_Example;

But now, I am ok with the fact that he did not get an error, but anyway it is always better to be coherent between signal and use unsigned only if it is needed.

Altera_Forum
Honored Contributor
15 years ago
A std_logic vector is really just a single bit.

std_logic_vector and unsigned are both an array of std_logic. As they are closely related types but not the same type, a type conversion is required, as you demonstrated.

The ONLY difference between unsigned and std_logic_vector is that they are declared separately. They are named differently for abstraction and understanding purposes. At the end of the day, they are synthesized into the same thing. Unsigned/signed have a package of useful function in the form of numeric_std that does arithmatic on them. Std_logic_vector does not have an IEEE package for arithmatic (until VHDL 2008).

--- Quote Start ---

But now, I am ok with the fact that he did not get an error, but anyway it is always better to be coherent between signal and use unsigned only if it is needed.

--- Quote End ---

So whats wrong with leaving it as unsigned?

Forum Discussion

13 Replies

Recent Discussions

I do not get an eMail with the generated license file

Installer cannot establish connection with SSL error

Quartus 13.1 including Signal Tap License

Quartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SG

Highlight similar instances of a selected word fails when scrolling