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Altera_Forum
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15 years ago

VHDL: DE2 Lab4 part1

Hello, I'm trying to follow lab 4, but am having problems. I was just told that my TFF was garbage, and it was pretty poetic, I wish i could post it for comic-relief, but anyway, I'd like to ask ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

This is correct, except that you don't need to put T signal in the sensitivity list of the process, because the output can change only when the reset is active, or on clock edge.