VHDL: DE2 Lab4 part1

I am not totally ok with you. Unsigned is std_logic but with a particular signification. You can assigned an unsigned to a std_logic (I discovered it just now, I did not think that it was possible), but not an unsigned to a std_logic_vector. Here there is an example, with this code :

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Example is
    port
    (
        clock        : in  std_logic;
        reset        : in  std_logic;
        outputScalar : out std_logic;
        outputVector : out std_logic_vector(9 downto 0)
        
    );
end Example;
architecture arch_Example of Example is
signal counter : unsigned(9 downto 0);
begin
    outputVector <= counter;
    outputScalar <= counter(0);
    process(reset, clock)
    begin
        if reset = '1' then
            counter <= (others => '0');
        elsif rising_edge(clock) then
            counter <= counter + 1;
        end if;
    end process;
end architecture arch_Example;

Quartus will give you the following error :

--- Quote Start ---

Error (10476): VHDL error at Example.vhd(22): type of identifier "counter" does not agree with its usage as "std_logic_vector" type

--- Quote End ---

And you have to use the following code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Example is
    port
    (
        clock        : in  std_logic;
        reset        : in  std_logic;
        outputScalar : out std_logic;
        outputVector : out std_logic_vector(9 downto 0)
        
    );
end Example;
architecture arch_Example of Example is
signal counter : unsigned(9 downto 0);
begin
    outputVector <= std_logic_vector(counter);
    outputScalar <= counter(0);
    process(reset, clock)
    begin
        if reset = '1' then
            counter <= (others => '0');
        elsif rising_edge(clock) then
            counter <= counter + 1;
        end if;
    end process;
end architecture arch_Example;

But now, I am ok with the fact that he did not get an error, but anyway it is always better to be coherent between signal and use unsigned only if it is needed.