Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

VHDL: DE2 Lab4 part1

Hello, I'm trying to follow lab 4, but am having problems. I was just told that my TFF was garbage, and it was pretty poetic, I wish i could post it for comic-relief, but anyway, I'd like to ask ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Put T in the sensitivity list will not change the behaviour, but it is possible that the logic generated be different, I am not sure on it. You can check that with the RTL viewer in Quartus after compilation.

About the counter, there are two things. The first is that I am not sure if you can put equation instead of a signal as a parameter of port map. I would advise to create a signal for inputs of each TFF, and moreover this will simplify the equation. Here you have an example : 


signal T : std_logic_vector(16 downto 0);
...
T(0) <= enable;
T(1) <= Qout(0) & T(0);
T(2) <= Qout(1) & T(1);
...
myTFFi  : entity work.myTFF port map( T(i), clk, rst, Qout(i));
Secondly, you declare Qout as unsigned, whereas output of TFF is std_logic, it is not coherent (Quartus did not give you an error about this ?) You can declare Qout as std_logic_vector, it is not needed to use unsigned since you don't make arithmetic operation on it.